If the title caught you off guard, I am sorry about that! But I am also glad it did because we need to talk about half cycle path. Consider the logic diagram below.
For the data launched by FF1 to be captured correctly at FF2, it should satisfy the setup time of FF2. Hence, setup timing check is always done at the next clock cycle. For hold timing check, the data at FF1 should be stable for a minimum time (Hold Time - th) so that it does not overwrite the data at FF2. Basically, the data at output of FF1 should only change after th time so that this data is registered by FF2 only in the next clock cycle and not in this clock cycle. This must be checked at launch edge of FF1, so hold timing check is zero cycle check and it does not depend on the frequency. But… the argument that hold time is independent of clock frequency is only true for zero cycle hold checks, i.e., when the hold check is performed on the same edge at which it is launched. Fortunately, most of the designs today only use zero cycle hold check. See the picture below for setup and hold check equation in that case.
If launch and capture is happening on different clock edges in a timing path, it is called a half cycle path. For example, using a positive edge triggered flop and a negative edge triggered flop creates a half cycle path. See the picture below for a clear explanation.
If you forget about half cycle path for a second and look at the picture above, there is no significant change in this when compared to the first logic diagram. The only change is in the skew, and we have a value for that now. Look at the picture below and try to guess the value of tskew.
I am sure you must have come up with the value of tskew to be T/2. Substituting that in the standard setup and hold equation, the equation becomes like this:
Looking at the equation, it is obvious now that the hold time is also depending on the frequency of operation. Even if you did not know the concept of half cycle path and you were shown the second logic diagram, you could have easily come up with this equation.
So, the next time if someone asks you if we can fix hold violation by varying frequency or not, your answer should be “it depends”. Is it a half cycle path? If yes, then we can. If no, the we cannot!
Signing-off with a question - In the second logic diagram, what if the first flip-flop was negative edge triggered and second flip-flop was positive edge triggered? Try it out! If you want to see the answer, you can find it in my Interview QnA PDF.
See you in the next one!